Propagation delay and RC timing

Every logic gate takes time to respond. When its input changes, the transistors that turn on must charge or discharge the capacitance hanging on the output through their own on-resistance and through the resistance of the wires. Lesson 5 treated delay in normalized units through logical effort; this lesson puts real resistances, capacitances and seconds on it. The same RC reasoning applies from the scale of a single transistor inside a chip to the scale of a reset line on a printed circuit board, and it sets the clock rate of every synchronous design.

Defining delay

Propagation delay is measured between the 50 percent points of the input and output waveforms. Because the pull-up and pull-down networks differ, a gate has two delays: t_PHL for an output falling from high to low and t_PLH for an output rising from low to high. Their average is often quoted as t_pd. Rise and fall times describe how quickly the output edge itself moves, usually between the 10 and 90 percent points, though some datasheets use 20 and 80 percent. A datasheet also distinguishes the maximum propagation delay, which the timing of a design must respect, from the minimum or contamination delay, which matters for hold-time checks in lesson 8.

The RC step response

The simplest model of a switching gate is a resistor charging a capacitor. When a step drives a resistance R into a capacitance C, the capacitor voltage approaches its final value exponentially with time constant τ = RC. The output crosses 50 percent after ln 2 time constants, about 0.69RC, and moves from 10 to 90 percent in ln 9, about 2.2RC. These two numbers are worth memorizing, because they convert any RC estimate into a delay or an edge rate.

The transistor is not really a linear resistor. When it first turns on, it is in saturation and delivers a nearly constant current; as the output approaches the rail it enters the linear region and behaves more like a resistor. Using an effective resistance, chosen so that the RC model gives the right delay, works well in practice. A common choice is the average of the on-resistance at the start and end of the transition, and cell libraries characterize each gate at many loads and input slopes so that tools do not rely on the approximation at all.

Delay therefore depends on the supply voltage, temperature and process corner discussed in lesson 1. With the alpha-power model from lesson 3, the drive current scales as (V_DD − V_t)^α, so delay scales roughly as C V_DD / (V_DD − V_t)^α. Lowering the supply from 3.3 V to 1.8 V with a 0.5 V threshold and α = 1.3 raises the delay by a factor of about 1.48 even though the swing is smaller, which is why microcontrollers that run their core from a low-voltage regulator also limit the maximum clock frequency in each voltage range.

Elmore delay for RC networks

Real signals pass through networks of resistances and capacitances: a driver, a chain of wire segments and several gate loads. Solving such a network exactly is tedious, but Elmore showed that a good estimate of the delay to any node is the sum, over every capacitor, of the capacitance times the resistance shared between the path from the source to that capacitor and the path from the source to the node of interest. For a simple chain, that shared resistance is just the total resistance from the source up to each capacitor.

Capacitors near the source are cheap, because only a little resistance lies between them and the driver; capacitors near the far end are expensive, because they charge through everything upstream. That asymmetry has practical consequences: a large load should be placed near a strong driver, and a branch that carries a heavy load should be fed from as close to the driver as possible. Elmore delay is the first moment of the impulse response and slightly overestimates the true 50 percent delay of a distributed line, but it is easy to compute by hand and is accurate enough to rank design choices.

Wires: resistance grows with length and so does capacitance

A uniform wire of length L has resistance rL and capacitance cL, where r and c are per unit length. Treated as a distributed line, its own delay is about 0.38rcL², roughly half the lumped estimate of 0.69RC, because each piece of capacitance sees only the resistance upstream of it. The square of the length is the critical point: doubling a wire's length quadruples its intrinsic delay. As processes shrink, wires get thinner and their resistance per unit length rises, so long on-chip wires have become slower relative to gates with every generation. A 10 mm wire in a modern process can take several nanoseconds unaided, while the gates that drive it switch in tens of picoseconds.

The cure is to break a long wire into segments and drive each one with a repeater, an inverter or buffer. Each segment's delay grows only with the square of its own length, so the total delay becomes linear in the length of the whole wire. The optimum spacing balances the delay of the repeaters themselves against the wire delay they eliminate; too few repeaters leave the quadratic term in place, too many add more gate delay than they save. Processors and large system chips contain thousands of repeaters, and the routing tools insert them automatically.

Board-level RC timing

On a printed circuit board, resistances are lower and capacitances higher, but the reasoning is identical. A microcontroller output pin at its high drive setting has an effective output resistance of perhaps 40 Ω. The trace from the NS-5 microcontroller to the radar module, with the radar input, totals about 13 pF, so the time constant is about 0.52 ns and the 10–90 percent rise time about 1.1 ns. At the lowest drive setting the output resistance may be ten times higher and the rise time correspondingly slower, which is often exactly what is wanted: slower edges radiate less and ring less, as lesson 12 explains.

Deliberately slow RC networks are useful too. A reset supervisor or a simple power-on reset holds a reset pin low while the supply settles, and an RC filter on a push-button input removes contact bounce before a Schmitt trigger squares the edge. For such networks the useful question is how long the capacitor takes to reach a particular threshold, not the 50 percent point.

Timing a synchronous path

Gate and wire delays add up along every path between flip-flops. In a synchronous design, the clock period must be long enough for a signal launched by one flip-flop to propagate through the slowest chain of logic and arrive at the next flip-flop before its setup time. The slowest such path is the critical path, and it sets the maximum clock frequency.

Static timing analysis tools check this inequality for every path in a design at the slow process corner, lowest voltage and highest temperature, and they check the companion hold constraint at the fast corner. Lesson 8 looks at the flip-flop side of the equation and at what happens when an asynchronous signal violates it. The practical result for a firmware or board designer is familiar: a microcontroller's maximum clock frequency is specified for each supply range and temperature range, and flash memory needs wait states once the clock period becomes shorter than its access time.

Computing delays with code

The code evaluates the Elmore delay of the example ladder and then studies a long on-chip wire. For each length it compares the unrepeated delay with the best number of repeated segments found by searching from 1 to 30. The unrepeated delay grows with the square of the length while the repeated delay grows linearly, at roughly 170 ps per millimeter for these parameters.

# Elmore delay of an RC ladder and of a long on-chip wire with repeaters
def elmore(R, C):
    # R[i], C[i]: resistance into node i and capacitance at node i (node 0 nearest the driver)
    t, r_path = 0.0, 0.0
    for r, c in zip(R, C):
        r_path += r                # resistance shared by the source and this node
        t += r_path * c
    return t

# driver 1 kOhm, three wire segments of 200 Ohm and 50 fF, gate load 20 fF at the far end
R = [1000, 200, 200, 200]
C = [10e-15, 50e-15, 50e-15, 50e-15 + 20e-15]
td = elmore(R, C)
print(f"Elmore delay to far end: {td*1e12:.0f} ps; 50% delay about {0.69*td*1e12:.0f} ps")

# long wire: r = 0.4 Ohm/um, c = 0.2 fF/um, driven by a repeater of 1 kOhm with 10 fF input
r, c = 0.4, 0.2e-15
Rd, Cd = 1000.0, 10e-15
for L_mm in (1, 2, 5, 10):
    Rw, Cw = r * L_mm * 1000, c * L_mm * 1000
    best = None
    for k in range(1, 31):
        seg = 0.69 * Rd * (Cw / k + Cd) + 0.69 * (Rw / k) * Cd + 0.38 * (Rw / k) * (Cw / k)
        t = k * seg
        if best is None or t < best[1]:
            best = (k, t)
    t1 = 0.69 * Rd * (Cw + Cd) + 0.69 * Rw * Cd + 0.38 * Rw * Cw
    print(f"{L_mm:2d} mm: no repeaters {t1*1e12:6.0f} ps, best {best[0]:2d} segments {best[1]*1e12:5.0f} ps")

Elmore delay to far end: 252 ps; 50% delay about 174 ps
 1 mm: no repeaters    178 ps, best  2 segments   170 ps
 2 mm: no repeaters    410 ps, best  4 segments   340 ps
 5 mm: no repeaters   1471 ps, best 11 segments   849 ps
10 mm: no repeaters   4454 ps, best 21 segments  1697 ps

The results confirm the hand calculation of 252 ps for the ladder and show the crossover at which repeaters pay off. At 1 mm, repeaters barely help; at 10 mm, they cut the delay by more than a factor of 2.5. On a board the same trade-off appears as the choice between one strong driver and a buffer placed partway along a long, heavily loaded net, such as a clock that fans out to many devices.