The CMOS inverter: transfer curve and noise margins

The inverter is the simplest CMOS gate and the template for all the others. One n-channel transistor connects the output to ground, one p-channel transistor connects it to the supply, and both gates are tied to the input. When the input is low, the n-channel device is off and the p-channel device is on, pulling the output to V_DD. When the input is high, the roles reverse and the output is pulled to ground. In either steady state one transistor is off, so no current flows from supply to ground. This lesson studies the inverter's voltage transfer characteristic, the curve of output voltage against input voltage, and uses it to define the switching threshold, the logic levels and the noise margins that make digital circuits robust.

Ines brings the topic to the bench with a practical question. The NS-5 microcontroller's datasheet promises that any input above 0.7 V_DD reads as a 1 and any input below 0.3 V_DD reads as a 0, and that its outputs reach within 0.4 V of the rails. Where do those numbers come from, and how much noise can a signal crossing the board pick up before a bit flips? The answers come straight from the inverter, because every input pin starts with one.

How the inverter works

Treating each transistor as a switch gives the logic function, but the interesting behaviour lies between the extremes. As the input rises from 0 V, nothing happens until it passes the n-channel threshold V_tn. Then the n-channel device begins to conduct while the p-channel device is still strongly on, and the output starts to fall slightly. Near the middle of the range both transistors are in saturation and the output swings steeply from high to low for a small change in input; this is the region of high gain. As the input approaches V_DD − |V_tp|, the p-channel device turns off and the output settles at 0 V. The result is the S-shaped transfer curve below.

The switching threshold

The switching threshold V_M is the input voltage at which the output equals the input, where the curve crosses the diagonal. At that point both transistors are in saturation and carry the same current. Setting the two saturation currents equal gives V_M in terms of the threshold voltages and the ratio of transistor strengths.

If the n- and p-channel devices have the same strength, r = 1 and, with equal threshold magnitudes, V_M sits at exactly V_DD/2. Because holes are less mobile, equal strength requires the p-channel device to be wider, by the ratio of k_n to k_p. A designer can deliberately skew V_M: a stronger p-channel device moves it up, a stronger n-channel device moves it down. Skewed inverters are used to detect a rising or falling edge early, and the input buffers of microcontroller pins are often designed with a Schmitt trigger, described below, rather than a single fixed threshold.

Logic levels and noise margins

A digital system must tolerate noise. Signals pick up crosstalk from neighbouring wires, ground bounce when many outputs switch, and supply ripple. The transfer curve shows how much noise a gate can absorb. The points where its slope equals −1 mark where the gain changes from less than one, where noise is attenuated, to greater than one, where it is amplified. The input voltages at those points define the input thresholds: V_IL, the highest input voltage guaranteed to be read as low, and V_IH, the lowest input voltage guaranteed to be read as high. Between them is a forbidden zone where the output is not a valid logic level.

The output levels V_OH and V_OL are the voltages a gate guarantees to produce for a high and a low. Noise margins compare what one gate guarantees to produce with what the next gate needs. The low noise margin is the amount by which a valid low output can be pushed up by noise before the next gate stops reading it as low; the high noise margin is the corresponding figure for a high output.

Datasheet values are deliberately more conservative than an ideal inverter's unity-gain points, because they must hold across process, voltage and temperature and include the loading on the output. A typical 3.3 V CMOS microcontroller specifies V_IH as 0.7 V_DD (2.31 V), V_IL as 0.3 V_DD (0.99 V), V_OH as V_DD − 0.4 V (2.9 V) at a few milliamps of load, and V_OL as 0.4 V. Those give noise margins of about 0.59 V in each direction. An unloaded CMOS output swings all the way to the rails, giving even bigger margins; the 0.4 V figures allow for the voltage dropped across the output transistor's on-resistance when it supplies current, as lesson 3 calculated.

Regeneration: why digital signals stay clean

The high gain in the middle of the transfer curve gives CMOS logic a property analog circuits lack: regeneration. Suppose a signal arrives slightly degraded, say a high level of 2.8 V instead of 3.3 V. The first gate's output is still very close to 0 V because the input is far into the low-gain region, and the second gate restores a clean 3.3 V. A chain of gates therefore pushes noisy signals back toward the rails at every stage instead of accumulating the noise. As long as the noise at each stage stays within the noise margin, information passes through any number of gates without error. This is the deep reason digital electronics scales to billions of gates.

Static and short-circuit current

In either steady state an ideal CMOS inverter draws no current, apart from leakage. During a transition, though, there is a brief interval when the input is between V_tn and V_DD − |V_tp| and both transistors conduct, so current flows straight from supply to ground. This short-circuit current is usually a small fraction of the total switching power, a few percent to perhaps twenty percent, provided input edges are fast. Slow input edges make it much worse, because the gate spends longer in the middle region. That is why an input pin left floating, or driven by a slowly rising signal such as an RC delay, can make a chip draw unexpected current: its input buffer sits in the conducting region. Part of the hidden sleep current that CMP-315 tracked down on the NS-4 came from unused pins left floating, and a single floating input can draw tens of microamps for exactly this reason; lesson 7 returns to the numbers.

Schmitt triggers: hysteresis at the input

A slowly changing or noisy input can cross the switching threshold several times as it passes through, making the output chatter. A Schmitt trigger adds hysteresis: the threshold for a rising input, V_T+, is higher than the threshold for a falling input, V_T−. Once the input has crossed V_T+ and the output has switched, it must fall all the way below V_T− before the output switches back. Noise smaller than the hysteresis band cannot cause extra transitions. CMOS Schmitt triggers use extra transistors that feed the output back to shift the threshold. CMP-240 built one from an op-amp for the NS-4's low-battery detector; many microcontroller pins can enable a Schmitt input buffer, and Ines turns it on for the NS-5's tamper switch input, which is connected through a long cable and an RC filter.

Computing the transfer curve

The program below finds the inverter's output for each input voltage by balancing the n- and p-channel currents with a bisection search, using the long-channel model from lesson 3 with a small channel-length modulation term so the steep region has finite gain. It then locates the unity-gain points and reports the switching threshold, the logic levels and the noise margins for the balanced inverter from the example.

VDD = 3.3
kn, kp = 300e-6, 120e-6       # A/V^2 (process parameters)
WLn, WLp = 2.0, 5.0           # sizing chosen so kn*WLn = kp*WLp
Vtn, Vtp = 0.5, 0.5           # magnitudes of thresholds
lam = 0.05                    # channel-length modulation, 1/V

def ids(k, wl, vgs, vds, vt):
    vov = vgs - vt
    if vov <= 0 or vds <= 0:
        return 0.0
    if vds < vov:
        return k * wl * (vov * vds - 0.5 * vds * vds) * (1 + lam * vds)
    return 0.5 * k * wl * vov * vov * (1 + lam * vds)

def vout(vin):
    lo, hi = 0.0, VDD
    for _ in range(60):
        mid = (lo + hi) / 2
        i_n = ids(kn, WLn, vin, mid, Vtn)
        i_p = ids(kp, WLp, VDD - vin, VDD - mid, Vtp)
        if i_n > i_p:
            hi = mid
        else:
            lo = mid
    return (lo + hi) / 2

N = 3301
vins = [VDD * i / (N - 1) for i in range(N)]
vouts = [vout(v) for v in vins]
slopes = [(vouts[i + 1] - vouts[i]) / (vins[i + 1] - vins[i]) for i in range(N - 1)]
VIL = next(vins[i] for i, s in enumerate(slopes) if s <= -1)
VIH = next(vins[i] for i in range(N - 2, -1, -1) if slopes[i] <= -1)
VM = next(vins[i] for i in range(N) if vouts[i] <= vins[i])
VOH, VOL = vout(VIL), vout(VIH)
print(f"switching threshold VM = {VM:.2f} V")
print(f"VIL = {VIL:.2f} V, VOH at VIL = {VOH:.2f} V")
print(f"VIH = {VIH:.2f} V, VOL at VIH = {VOL:.2f} V")
print(f"NM_L = VIL - VOL = {VIL - VOL:.2f} V")
print(f"NM_H = VOH - VIH = {VOH - VIH:.2f} V")
print(f"peak gain = {min(slopes):.1f}")

switching threshold VM = 1.65 V
VIL = 1.32 V, VOH at VIL = 3.01 V
VIH = 1.98 V, VOL at VIH = 0.29 V
NM_L = VIL - VOL = 1.03 V
NM_H = VOH - VIH = 1.04 V
peak gain = -37.7

The balanced inverter switches at 1.65 V, with unity-gain points at about 1.32 V and 1.98 V and noise margins just over 1 V on each side. That is better than the 0.59 V a datasheet promises, because the simulation has no load current and no process or temperature spread. The peak gain of about −38 shows how steep the middle of the curve is. Change WLp to 2.0 in the code and the threshold drops to about 1.39 V, matching the worked example, and the low noise margin shrinks.