DCE-210 · Lesson 11 of 12 · 37 min
High-performance and AI cluster networks
Training a large AI model is one enormous calculation spread across thousands, sometimes hundreds of thousands, of accelerators. No single chip has enough memory or speed, so the model and the data are divided among them, and the accelerators must constantly exchange results. If the network cannot keep up, the most expensive computers ever built sit idle, waiting. In an AI training cluster the network is not a supporting system; it is part of the computer.
High-performance computing (HPC) clusters for science and engineering have faced the same problem for decades, and AI networks borrow much from them. This chapter explains why AI training is so demanding on the network, the three networks inside an AI cluster, the technologies used (NVLink and other scale-up links, InfiniBand, and RDMA over Ethernet), how cluster fabrics are built and sized, and what all this means for the data center: thousands of optics, enormous fiber counts, high power and tight distance limits.
Why AI training stresses the network
A neural network is trained in steps. In each step, a batch of training examples flows forward through the model, the error is measured, and gradients (the direction in which each parameter should change) flow backward. Then every parameter is updated. A large model has hundreds of billions of parameters.
The simplest way to use many accelerators is data parallelism: every accelerator holds a full copy of the model and processes a different slice of the batch. After the backward pass, each accelerator has its own gradients, and they must be averaged across all accelerators before anyone can update the model. That averaging is a collective operation called all-reduce, and every accelerator must finish it before the next step begins. Larger models also split the model itself across accelerators, using tensor parallelism (splitting individual layers), pipeline parallelism (placing different layers on different accelerators) and expert parallelism (spreading the "experts" of a mixture-of-experts model), each with its own communication pattern.
Three features make this traffic unlike ordinary data center traffic:
- It is synchronized. Thousands of accelerators finish computing at the same moment and then all transmit at full speed at once. There is no statistical smoothing of the kind that justifies oversubscription in a general-purpose fabric.
- It is made of huge flows. Gradients are gigabytes, sent between the same pairs of accelerators again and again. These elephant flows defeat the hash-based load balancing described in Lesson 3.
- The slowest link sets the pace. A collective finishes only when the last accelerator finishes. One congested link, one failing optic or one slow switch port delays the entire job. Engineers talk about tail latency and job completion time rather than average throughput.
In a well-designed cluster, communication overlaps with computation and takes a modest share of each step. In a poorly designed one, accelerators may spend a large fraction of their time waiting, which on a cluster costing billions of dollars is an enormous waste.
The ring all-reduce
A classic way to perform an all-reduce among \(N\) accelerators is to arrange them in a logical ring. The gradient buffer of size \(S\) is split into \(N\) chunks. In the first phase (reduce-scatter), each accelerator repeatedly sends one chunk to its neighbor and adds the chunk it receives, so after \(N-1\) steps each accelerator holds one fully summed chunk. In the second phase (all-gather), the summed chunks travel around the ring for another \(N-1\) steps until everyone has all of them. Each accelerator sends a total of:
For large \(N\) this approaches \(2S\): each accelerator sends about twice the size of the gradients, almost regardless of how many accelerators there are. The time is roughly \(D\) divided by each accelerator's network bandwidth, plus latency for each of the \(2(N-1)\) steps. Real libraries such as NCCL use rings, trees and hierarchical schemes chosen to suit the topology, but the ring shows the key point: the bandwidth per accelerator directly sets the communication time.
Worked problem
How long does gradient synchronization take?
A model has 70 billion parameters, and gradients are stored in 16-bit format (2 bytes each). Estimate the ring all-reduce time (bandwidth term only) for (a) 8 GPUs in one server connected by NVLink at about 900 GB/s per GPU in each direction, and (b) 1024 GPUs connected by a 400 Gb/s network adapter each.
Show solution
- Gradient size: \(S = 70 \times 10^9 \times 2 = 140\) GB.
- (a) \(D = 2 \times 7/8 \times 140 = 245\) GB. Time \(= 245 / 900 = 0.27\) s.
- (b) \(D = 2 \times 1023/1024 \times 140 = 279.7\) GB. Network bandwidth = 400 Gb/s = 50 GB/s.
- Time \(= 279.7 / 50 = 5.6\) s.
Answer: About 0.27 s inside the NVLink server but about 5.6 s across the 1024-GPU network, twenty times longer. In practice, frameworks shard the gradients and optimizer state, overlap communication with computation and keep the heaviest traffic inside the fast scale-up domain, but the example shows why per-accelerator bandwidth and the size of the scale-up domain matter so much.
The three networks of an AI cluster
A modern AI cluster has three distinct networks, each with its own purpose, technology and cabling:
- The scale-up network connects a small group of accelerators so tightly that they behave almost like one large accelerator with shared memory. It runs at very high bandwidth and very low latency over short distances, usually within a server or a rack. Examples are NVIDIA's NVLink, AMD's Infinity Fabric and the open UALink standard (version 1.0 published in 2025). In a rack-scale system such as NVIDIA's GB200 NVL72, NVLink switches connect 72 GPUs, each with about 1.8 TB/s of total NVLink bandwidth, over thousands of short copper cables in the rack spine. A single rack like this can draw about 120 kW or more and needs liquid cooling.
- The scale-out or back-end network connects the scale-up domains to each other across the cluster. Each accelerator usually has its own network adapter at 400 or 800 Gb/s. This is the large, non-blocking fabric this chapter focuses on, built with InfiniBand or with Ethernet tuned for AI.
- The front-end network connects the cluster to storage, to the rest of the data center, to users and to the internet. It carries training data in, model checkpoints out to storage, and management traffic. It is a conventional leaf-spine Ethernet fabric (Lesson 3), typically with oversubscription and lower bandwidth per server than the back-end.
A separate out-of-band management network, as in Lesson 1, connects every server's management controller, switch and power distribution unit, bringing the total to four.
Scale-out technologies: InfiniBand and Ethernet
RDMA
Ordinary networking passes data through the operating system: the application copies data into kernel buffers, the TCP stack processes it, and the network card sends it, with the reverse at the other end. This costs CPU time and adds latency. Remote direct memory access (RDMA) lets a network adapter read from or write into the memory of a remote machine directly, bypassing the operating system and the CPU on both sides. With GPUDirect RDMA, the adapter reads and writes GPU memory directly, so gradients go from one accelerator's memory to another's with no copies through host memory. Every AI back-end network uses RDMA.
InfiniBand
InfiniBand is a networking technology designed from the start for HPC. It has its own switches, adapters and protocols, controlled by a central subnet manager that computes routes for the whole fabric. Its key feature is credit-based, lossless flow control: a sender transmits only when the receiver has advertised buffer space, so packets are never dropped because of congestion. Current generations are NDR (400 Gb/s per port) and XDR (800 Gb/s). InfiniBand switches can also perform some collective operations inside the network, reducing the data the accelerators must exchange. InfiniBand has long dominated the largest AI training clusters, and it is supplied mainly by one vendor.
Ethernet for AI: RoCE and Ultra Ethernet
Ethernet has many suppliers, a huge ecosystem and the operational familiarity of every data center team, and it now carries a large and growing share of AI back-end networks. RDMA runs over Ethernet using RoCE v2 (RDMA over Converged Ethernet), which places RDMA traffic inside UDP/IP packets so it can be routed across a leaf-spine fabric.
The challenge is that RDMA performs badly when packets are lost, and ordinary Ethernet drops packets when buffers overflow. AI Ethernet fabrics address this with:
- Priority Flow Control (PFC, IEEE 802.1Qbb), which lets a switch tell its neighbor to pause one class of traffic briefly when its buffers fill, making that class lossless.
- Explicit Congestion Notification (ECN), in which switches mark packets when queues start to build, and the endpoints slow down before losses occur.
- Advanced load balancing: spraying packets of a flow across many paths, or adaptive routing that steers traffic around congested links, instead of the static per-flow ECMP hash that elephant flows defeat.
The Ultra Ethernet Consortium, an industry group, published version 1.0 of its specification in 2025, defining a new transport designed for AI and HPC over Ethernet with multipath packet spraying, modern congestion control and tolerance of out-of-order delivery, aiming to deliver InfiniBand-class performance on standard Ethernet hardware.
Building the back-end fabric
Fat trees and non-blocking design
AI back-end fabrics are Clos networks like those in Lesson 3, but built non-blocking (1:1) at every layer. In the HPC world, a non-blocking Clos network is often called a fat tree, because the bandwidth stays the same (the branches stay "fat") all the way to the top. With switches of radix \(k\) (ports per switch), each leaf uses half its ports for accelerators and half for uplinks. A two-tier non-blocking fat tree supports:
and a three-tier fat tree supports:
Switch radix therefore matters enormously. Doubling the radix quadruples the size of a two-tier fabric and multiplies a three-tier fabric by eight, while each extra tier adds switches, optics, latency and cost. This is why switch vendors push for higher radix as hard as for higher speed, and why a 51.2 Tb/s switch is often run as 128 ports of 400 Gb/s rather than 64 of 800 Gb/s in AI fabrics.
Worked problem
Sizing a two-tier AI fabric
An AI fabric uses switches with 64 ports of 400 Gb/s, and each GPU has one 400 Gb/s adapter. How many GPUs can a non-blocking two-tier fabric connect, and how many leaf and spine switches does it need? How large would a three-tier fabric be?
Show solution
- Two-tier endpoints: \(k^2/2 = 64^2/2 = 2048\) GPUs.
- Each leaf: 32 ports down to GPUs, 32 up. Leaves needed: \(2048/32 = 64\).
- Each leaf has one link to each spine, so there are 32 spines, each with 64 ports (one per leaf).
- Three-tier endpoints: \(k^3/4 = 64^3/4 = 65{,}536\) GPUs.
Answer: 2048 GPUs with 64 leaves and 32 spines (96 switches) in two tiers; up to 65,536 GPUs in three tiers. With 128-port switches the two-tier limit rises to 8192 GPUs.
Worked problem
The optics bill
For the 2048-GPU fabric above, assume every link is optical, with one transceiver at each end drawing 15 W. How many transceivers are there, and how much power do they draw? Compare with GPU servers drawing about 1.4 kW per GPU, including their share of the server.
Show solution
- GPU-to-leaf links: 2048. Leaf-to-spine links: \(64 \times 32 = 2048\). Total 4096 links.
- Transceivers: \(2 \times 4096 = 8192\).
- Optics power: \(8192 \times 15 = 122{,}880\) W, about 123 kW.
- GPU servers: \(2048 \times 1.4 = 2867\) kW.
- Ratio: \(123 / 2867 = 4.3\%\).
Answer: 8192 transceivers drawing about 123 kW, roughly 4% of the IT load, before counting the switches themselves. In a 100,000-GPU cluster the optics alone reach several megawatts, which is why the industry is pursuing linear-drive pluggable optics and co-packaged optics that place the optical engines next to the switch chip to cut power.
Rail-optimized topology
AI servers typically hold eight accelerators, each with its own network adapter. In a rail-optimized design, accelerator number 0 in every server connects to one set of leaf switches (rail 0), accelerator 1 in every server to rail 1, and so on, up to rail 7. Communication libraries arrange collectives so that most traffic passes between accelerators with the same index in different servers, which then needs only one hop through a rail leaf. Traffic between different indices moves first across the fast NVLink inside the server and then along the right rail. Rail-optimized designs reduce the load on the spine layer and the latency of the most common transfers.
Rail designs have a physical consequence: each server sends eight cables to eight different leaf switches, often in a different rack, rather than to one top-of-rack switch. Leaves for a group of GPU racks are usually placed together in network racks at the end or middle of the rows, and every GPU rack has dozens of fibers running to them.
What AI networks mean for the facility
AI clusters change the data center design brief in ways that land directly on the facility engineer:
- Distance limits shape the floor plan. Copper scale-up links reach only a couple of meters, which is why scale-up domains are built as single racks or adjacent racks. Back-end optics have reach limits too, and latency adds up with fiber length (about 5 ns per meter). Designers lay out GPU racks, network racks and spines to keep every run within the reach of the chosen optics, often arranging a cluster as compact "pods" or "scalable units" with the network at the center.
- Fiber counts are enormous. A cluster of tens of thousands of GPUs can have hundreds of thousands of fiber terminations. Overhead tray capacity, patch panels and installation labor become major cost and schedule items, and pre-terminated MPO trunks and high-count ribbon cables are standard.
- Network power and cooling are substantial. Switches and optics can add several percent to the IT load, network racks may draw 20 to 40 kW, and some new switch platforms are liquid cooled like the accelerators.
- Rack density changes everything else. Scale-up racks at 100 kW and above require direct-to-chip liquid cooling (DCE-330), heavy power distribution (DCE-310) and floors or slabs rated for racks weighing well over a metric ton (DCE-430).
- Reliability is about the job, not the link. Because one failed link can stall a training job across thousands of accelerators, operators monitor every optic, keep spares on site and design for fast replacement. Optics, and especially the dust on their connectors, are among the most common failure points in a cluster.
- Storage and checkpoints need their own bandwidth. Training jobs periodically save checkpoints, the full model and optimizer state, so they can restart after a failure. These bursts travel over the front-end or a dedicated storage network.
Worked problem
Checkpoint bandwidth
A 70-billion-parameter model is trained with an optimizer that keeps about 14 bytes of state per parameter (16-bit weights, 32-bit master weights and two 32-bit optimizer moments). The storage system can absorb 1 Tb/s in total. How large is a checkpoint and how long does it take to write?
Show solution
- Checkpoint size: \(70 \times 10^9 \times 14 = 980\) GB.
- Storage bandwidth: 1 Tb/s = 125 GB/s.
- Time: \(980 / 125 = 7.8\) s.
Answer: About 980 GB, written in roughly 8 seconds at 1 Tb/s. Larger models and more frequent checkpoints push storage networks to many terabits per second, which shapes the front-end design.
Beyond training
Inference (running trained models to answer requests) is a growing share of AI computing. A single inference request usually runs within one server or one scale-up domain, so inference clusters need less back-end bandwidth than training clusters and rely more on the front-end network and on latency to users. Large models served at scale still split work across accelerators, however, and newer serving designs move intermediate results between separate groups of accelerators, so inference fabrics are becoming more demanding too.
At the other extreme, the largest training efforts are now spreading across multiple buildings and even multiple campuses, linked by massive DWDM systems (Lesson 9) carrying hundreds of terabits per second between sites. Distributing training across sites hundreds of kilometers apart brings the latency limits of Lesson 7 into the design of the training software itself.
Common mistakes
MistakeApplying general-purpose oversubscription ratios to an AI back-end fabric.
InsteadTraining traffic is synchronized; back-end fabrics are built non-blocking (1:1).
MistakeJudging an AI network by average throughput.
InsteadCollectives wait for the slowest participant; tail latency and job completion time matter most.
MistakeAssuming ordinary Ethernet works for RDMA without tuning.
InsteadRoCE needs lossless or congestion-controlled operation (PFC, ECN) and better load balancing than static ECMP.
MistakeTreating the cluster as one network.
InsteadThere are separate scale-up, scale-out (back-end), front-end and management networks, each with its own cabling and limits.
MistakeLeaving optics power out of the IT load.
InsteadThousands of 10–20 W transceivers add several percent to IT power and heat.
Summary and key terms
- AI training traffic is synchronized, made of huge flows, and limited by the slowest link.
- A ring all-reduce sends \(2(N-1)S/N \approx 2S\) bytes per accelerator; time depends directly on per-accelerator bandwidth.
- AI clusters have scale-up (NVLink, UALink), scale-out back-end (InfiniBand or AI Ethernet), front-end and management networks.
- RDMA moves data directly between memories without the CPU; RoCE v2 carries it over Ethernet with PFC, ECN and advanced load balancing.
- Back-end fabrics are non-blocking fat trees: \(k^2/2\) endpoints in two tiers and \(k^3/4\) in three.
- Rail-optimized designs connect GPU \(i\) in every server to rail leaf \(i\), keeping most traffic to one hop.
- Thousands of optics add several percent to IT power; fiber counts, reach limits and rack density drive the floor plan.
- Checkpoints and data ingestion need substantial front-end and storage bandwidth.
- Data parallelism
- Training with a full copy of the model on each accelerator, each processing different data, with gradients averaged every step.
- All-reduce
- A collective operation that sums (or averages) data from all participants and gives every participant the result.
- Collective operation
- A communication pattern involving a whole group of accelerators, such as all-reduce, all-gather or all-to-all.
- Tail latency
- The delay experienced by the slowest operations, which governs synchronized workloads.
- Scale-up network
- A very high-bandwidth, short-reach network joining a small group of accelerators into one domain.
- Scale-out (back-end) network
- The cluster-wide fabric connecting scale-up domains for training traffic.
- Front-end network
- The network connecting a cluster to storage, users and the rest of the data center.
- NVLink
- NVIDIA's high-bandwidth interconnect between GPUs within a server or rack.
- RDMA
- Remote direct memory access: moving data directly between machines' memories without the CPU or operating system.
- InfiniBand
- A lossless, credit-based networking technology designed for HPC and widely used in AI clusters.
- RoCE v2
- RDMA over Converged Ethernet, version 2: RDMA carried in UDP/IP packets over Ethernet.
- Priority Flow Control (PFC)
- An Ethernet mechanism that pauses one traffic class to prevent buffer overflow and loss.
- Fat tree
- A non-blocking Clos network in which bandwidth is maintained at every tier.
- Rail-optimized topology
- A design connecting accelerator number \(i\) of every server to the same group of leaf switches.
- Co-packaged optics
- Optical engines placed in the same package as a switch chip to reduce power and electrical loss.
- Checkpoint
- A saved copy of a model and its training state, used to restart after a failure.
Practice problems
Work each problem on paper first, then reveal the answer to check.
How much data does each accelerator send in a ring all-reduce of 10 GB among 16 accelerators?
Show answer
2 × 15/16 × 10 = 18.75 GB.
Estimate the bandwidth time for the previous all-reduce if each accelerator has an 800 Gb/s adapter.
Show answer
800 Gb/s = 100 GB/s; 18.75 ÷ 100 = 0.19 s.
How many GPUs can a non-blocking two-tier fat tree connect with 128-port switches? How many with three tiers?
Show answer
128²/2 = 8192 in two tiers; 128³/4 = 524,288 in three tiers.
For a two-tier fabric with 128-port switches, how many leaves and spines are needed at full size?
Show answer
8192 ÷ 64 = 128 leaves, each with 64 uplinks, so 64 spines.
A cluster has 16,384 GPUs, each with one 800 Gb/s adapter connected by an optical link to its leaf. How many transceivers do those GPU links need, and at 16 W each, how much power?
Show answer
16,384 links × 2 = 32,768 transceivers × 16 W = 524 kW.
Why are AI back-end fabrics built non-blocking while front-end fabrics are often 3:1?
Show answer
All accelerators transmit at full rate at the same time during collectives, so any oversubscription slows the job. Front-end traffic (storage, users) is burstier and statistically shared.
What two mechanisms help make Ethernet suitable for RDMA traffic, and what does each do?
Show answer
PFC pauses a traffic class to prevent buffer overflow and loss; ECN marks packets as queues build so senders slow down before loss occurs.
In a rail-optimized design with 8 GPUs per server and 256 servers, how many GPUs connect to each rail?
Show answer
One GPU per server per rail: 256 GPUs per rail.
A model with 400 billion parameters keeps 14 bytes of training state per parameter. How long does a checkpoint take at 4 Tb/s?
Show answer
400 × 10⁹ × 14 = 5.6 TB; 4 Tb/s = 500 GB/s; 5600 ÷ 500 = 11.2 s.
Give three ways AI clusters change the facility design compared with a general-purpose data hall.
Show answer
Any three of: very high rack density needing liquid cooling; heavy power distribution; strict distance limits shaping the floor plan around the network; enormous fiber counts and tray capacity; significant network power; heavier racks and floor loads; storage bandwidth for checkpoints.
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